Verification is the most complex and challenging part in the design of system-on-chip (SoC) devices and reusable IP blocks. Verification ensures that functional defects in the design is caught at an earlier stage of the design process, helping to save cost. In the Verification process a series of steps are implemented to ensure that the given hardware is working as expected.
The most advanced form of verification technique is UVM-Universal Verification Methodology, which addresses how to build a scalable, predictable and reusable environment enabling users to take full advantage of assertions, reusability, testbench automation, coverage, formal analysis, and other advanced technologies to help solve their RTL and system-level verification problems. The UVM technique enables all SoC and IP projects to establish an effective, efficient and predictable verification process that is based upon the experience of leading industry experts from ARM, Synopsys, and many others.
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