Design & Verification
Ensuring Digital Excellence Through Rigorous Validation and Innovation.

- Interconnect Validation

- Interconnect Design
- Memory

- RV32G Core
- RV64GV Core

- Architecture Design
- Controller Design
- Platform Level Testing

- APB
- AXI4
- AXI4 Stream
- I2C
- SPI
- UART

- Memory Subsystems
- DMA Controller
- Interconnect
- Register Interface
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APB to AXI Bus Bridge
Ishraq Tashdid, Junior VLSI Engineer
AXI Memory Controller
Ishraq Tashdid, Junior VLSI Engineer