DSi VLSI | One-stop RTL-to-GDSII Solution

VLSI

Seamless, Secure, Scalable:
Your Digital Landscape Refined Building Tomorrow's Infrastructure Today

SERVICES

Our Services

Digital SoC DV with tailored UVM and VIP models

SV design, UVM verification, and VIP models for custom digital hardware

Physical chip design, verification, and testing

Backend services including semi-custom layout, verification, PnR, and testing

IC Package Design

Safeguard Your Device's Core with Our Expertise for Enhanced Device Protection

Bridge the gap between hardware and software

Application driven system development for IoT, 5G, and smart devices also

Infrastructural build setup and maintenance

Amazon AWS and other secure infrastructure capability with robust IT support

ACHIEVEMENTS

Recent Achievements

RISC V processor coresDelivered validated designs of various types of RISC-V processor cores including CVA6 and PULP with SPE verification for vector operations and FPU pipeline verification

RISC-V ISA verificationCustom ISA verification for vector operations utilizing Google riscv-test and riscv-tourture using SPIKE model on CVA6 RISC-V processor architecture

Memory Subsystem modelsDelivered validated designs of various types of RISC-V processor cores including CVA6 and PULP with SPE verification for vector operations and FPU pipeline verification

Digital communicationDeveloped multiple digital communication port protocol hardware designs including AXI (AXI4, AXI4Stream, AXI4lite), APB, Ethernet, and serial (USB, I2C, SPI, UART)

Advanced Bus bridgesDesign and verification of bus bridges, adapters, and converters for AXI4-to-APB, AXI4stream-to-AXI4, AXI-Xbar, SerDes, etc.

Expertise in design and verification

Expertise in diverse DV

01
SV for hardware design and linear verification
02
UVM test architecture for VIP and complex hardware verification
03
SystemC verification for complete system model simulation
04
Integration and automation with scripting languages such as C++, Python, and bash makefile scripts
05
RISC ISA verification on CVA6 processors using SPIKE model
06
RISC-V assembly and machine code simulation and validation for functionality
07
SV, Verilog, and VHDL support for FPGA programming
08
C, C++, and python support for microcontrollers such as ESP32 with freeRTOS
09
Tailored and AI-driven backend testing and verification for layout, PnR, and physical testing